![]() The reason is that verilog evaluates them according to the above rules and figures out that the same wire is driven by multiple devices with different values. Most likely you got 'x' on such wires in your case. Verilog is very picky about how such wires are evaluated. In your case you instantiate a few modules multiple times passing the same wire as an output wire. Modules are only containers for those device models and are never evaluated as a whole. As a result, sequence of evaluation of device models depends on the values of the signals in the model. This means that a certain procedural block gets evaluated if and only if at least one of its input's value changes. In order to simulate parallel behavior of hardware verilog employs event-driven technique. ![]() The only sequential programming piece in verilog exist within procedural blocks which describe behavior of hardware devices. They are also connected by a set of wires inside the module. They describe connections inside modules and low level hardware devices. Module itself is described in terms of continuous assignments and procedural blocks, e.g., 'always' blocks. Module instances are connected with each other by "wires" which transfer signal values. They cannot be 'executed' nor can they be execute in a 'sequence'. ![]() Modules describe hardware hierarchy by hierarchy of instances and nothing else. Verilog tries to mimic hardware behavior by providing hardware modules. The result of the hardware evaluation depends on the input signals, connections between elements and the previous state. There is nothing sequential in hardware itself. As such, it allow description of the structure of hardware systems. Verilog is a "hardware description language", it is not a generic programming language.
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